1. Field of the Invention
The present invention relates to a semiconductor device and, in particular, to a semiconductor device having substrate bias control capability.
2. Description of the Related Art
As the scale of integration of semiconductor integrated circuits has increased, standard-cell-based layout design has been made in which a cell library of standard cells, which are logic circuits such as inverter circuits and buffer circuits, is created and used. In order to increase the speed of operation of semiconductor integrated circuits and to control leakage current, substrate bias control is used which controls the source potential of a transistor and substrate potential, that is, the potential of a well region, are controlled by using separate power supplies. The potential required for the substrate bias control is called substrate bias potential. Increasing the substrate bias potential increases the threshold voltage, and therefore leakage current and power consumption can be reduced. Decreasing the substrate bias potential decreases the threshold voltage, and therefore the speed of operation of transistors can be increased.
The substrate bias potential is provided through a substrate bias control line provided separately from an ordinary power supply line. Accordingly, standard cells to which substrate bias control is applied requires terminals and lines for providing the substrate bias potential to the standard cells, while power consumption is reduced due to reduction in leakage current and operation speed can be increased. Therefore, a problem with standard cells to which substrate bias control is applied arises in footprint.
In order to solve the problem, a semiconductor integrated circuit has been proposed which is provided with standard cells without terminals and lines for providing substrate bias and spacer cells or filler cells for keeping a well potential at a fixed level. The standard cells are disposed first and then the spacer cells or filler cells are disposed in unoccupied regions for keeping the substrate bias potential of well regions of the standard cells without substrate bias terminals and lines at a fixed level (see for example Japanese Patent Application Laid-Open No. 2006-173478).
In a semiconductor integrated circuit, signal lines are densely provided in narrow regions between an input/output unit and functional block and between functional blocks for passing signals from a core logic unit to the input/output unit. In addition, standard cells included in circuitry constituting a random logic are disposed in the narrow regions.
That is, standard cells such as buffer circuits also called repeaters that function as elements for shaping signal waveforms distorted by transmission over a long-distance line are also disposed in the narrow regions. Such standard cells are disposed only in locations in the narrow regions where the cells are needed and the density of the standard cells is low as compared with standard cells provided in a core logic unit, for example. If spacer cells or filler cells are disposed in the unoccupied space between the sparsely disposed standard cells as in the above semiconductor integrated circuit proposed, the density of spacer of filler cells will be so high that space for disposing signal lines cannot be provided.